| Job Description: | Job Description –
In this role, you will participate in the design and verification of leading-edge multimillion gate, 45nm / 28nm (or smaller geometry) ASICs. Our team develops custom switching / routing ASICs for use in Cisco’s flag bearer products like the Catalyst 6500, Nexus 7000, MDS9000, Catalyst 4500, Catalyst 3750 switching platforms and GSR and CRS-3, ASR9000, ASR90X routing platforms as well as ASICs critical to strategic product areas being aggressively pursued by Cisco. These silicon chips are used to build high density 10Gbps/40Gbps or higher speed multi-protocol switches / routers. The ASICs have the network and fabric interfaces and have a rich feature set that includes multiple high bandwidth ports, low-latency, on chip-buffers, queuing, scheduling, congestion management. The ASICs support multiple protocols such as standards based Ethernet and Fibre Channel as well as emerging standards like Data Center Ethernet, Fibre Channel Over Ethernet, and TRILL.
Responsibilities:
You will participate in the design and verification process starting with high-level conceptual and architectural discussions and ending with micro architecture and design partition within the ASIC. You will find that design courses such as digital logic, computer architecture and organization, and network/communication architecture will be very helpful throughout this stage. Datapath pipelines, state-machines, and computer arithmetic elements are key components within the ASIC.
Skills:
•Hardware design, the test/verification environment is designed using an object-oriented framework designed in C++ so you will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as Verilog HDL, C, and C++.
•You will aid in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components.
•Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based verilog simulators.
•Problem solving skills and out-of-the-box thinking to create area and power efficient hardware designs as well as reusable C++ classes for the verification and simulation environments.
•Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members.
•BSEE is required/MSEE is preferred.
•Team-player, can-do attitude will work well in a group environment while still being able to contribute on an individual basis and you will find that you'll have lots of fun and thrive in this environment if you enjoy being challenged, learning new ideas, and push yourself to achieve aggressive technology goals. |
